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DDR SDRAM (Rev.0.1) Jun,'00 Preliminary
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
PRELIMINARY
Some of contents are subject to change without notice.
DESCRIPTION
M2S28D20ATP is a 4-bank x 8388608-word x 4-bit, M2S28D30ATP is a 4-bank x 4194304-word x 8-bit, M2S28D40ATP is a 4-bank x 2097152-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output data and data strobe are referenced on both edges of CLK. The M2S28D20/30/40ATP achieves very high speed data rate up to 133MHz, and are suitable for main memory in computer systems.
FEATURES
- Vdd=Vddq=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each positive CLK edge; - data and data mask referenced to both edges of DQS - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2.0/2.5 (programmable) - Burst length- 2/4/8 (programmable) - Burst type- sequential / interleave (programmable) - Auto precharge / All bank precharge controlled by A10 - 4096 refresh cycles /64ms (4 banks concurrent refresh) - Auto refresh and Self refresh - Row address A0-11 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16) - SSTL_2 Interface - 400-mil, 66-pin Thin Small Outline Package (TSOP II) - FET switch control(/QFC) for x4/ x8 - JEDEC standard
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DDR SDRAM (Rev.0.1) Jun,'00 Preliminary
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM PIN CONFIGURATION(TOP VIEW)
x4 x8 x16
VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC NC VDDQ NC NC VDD NU,/QFC NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD NU,/QFC NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM /CLK CLK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS NC VREF VSS DM /CLK CLK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC NC VSSQ DQS NC VREF VSS DM /CLK CLK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS
66pin TSOP(II)
400mil width x 875mil length 0.65mm Lead Pitch
ROW A0-11 Column A0-9,11(x4) A0-9 (x8) A0-8 (x16)
CLK,/CLK CKE /CS /RAS /CAS /WE DQ0-7 DQS DM /QFC Vref
: Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Data I/O : Data Strobe : Write Mask : FET Switch Control for x4/x8 : Reference Voltage
A0-11 BA0,1 Vdd VddQ Vss VssQ
: Address Input : Bank Address Input : Power Supply : Power Supply for Output : Ground : Ground for Output
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MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
BLOCK DIAGRAM
DLL
DQ0 - 15
/QFC for x4/x8 UDQS,LDQS
I/O Buffer
QFC&QS Buffer
Memory Array Bank #0
Memory Array Bank #1
Memory Array Bank #2
Memory Array Bank #3
Mode Register Control Circuitry
Address Buffer Clock Buffer A0-11 BA0,1 CLK, /CLK CKE
Control Signal Buffer
/CS /RAS /CAS /WE
UDM, LDM
Type Designation Code
This rule is applied to only Synchronous DRAM family.
M 2 S 28 D 3 0 A TP -75
Speed Grade 10: 125MHz@CL=2.5,100MHz@CL=2.0 75: 133MHz@CL=2.5,100MHz@CL=2.0 Package Type TP: TSOP(II) Process Generation Function Reserved for Future Use Organization 2 n 2: x4, 3: x8, 4: x16 DDR Synchronous DRAM Density 28: 128M bits Interface V:LVTTL, S:SSTL_3, _2 Memory Style (DRAM) Mitsubishi Main Designation
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MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
PIN FUNCTION
SYMBOL TYPE DESCRIPTION Clock: CLK and /CLK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CLK and negative edge of /CLK. Output (read) data is referenced to the crossings of CLK and /CLK (both directions of crossing). Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE becomes asynchronous input. Self refresh is maintained as long as CKE is low. Chip Select: When /CS is high, any command means No Operation. Combination of /RAS, /CAS, /WE defines basic commands. A0-11 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-11. The Column Address is specified by A0-9,11(x4), A0-9(x8) and A0-8(x16). A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, all banks are precharged. Bank Address: BA0,1 specifies one of four banks to which a command is applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands. Data Input/Output: Data bus Data Strobe: Output with read data, input with write data. Edgealigned with read data, centered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS correspond to the data on DQ8-DQ15 FET Control: Optional. Output during every Read and Write access. Can be used to control isolation switches on modules. Open drain output. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0DQ7; UDM corresponds to the data on DQ8-DQ15. Power Supply for the memory array and peripheral circuitry. VddQ and VssQ are supplied to the Output Buffers only. SSTL_2 reference voltage.
CLK, /CLK
Input
CKE
Input
/CS /RAS, /CAS, /WE
Input Input
A0-11
Input
BA0,1 DQ0-15(x16), DQ0-7(x8), DQ0-3(x4),
Input
Input / Output
DQS
Input / Output
/QFC
Output
DM
Input
Vdd, Vss VddQ, VssQ Vref
Power Supply Power Supply Input
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MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
BASIC FUNCTIONS
The M2S28D20/30/40ATP provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and precharge option, respectively. To know the detailed definition of commands, please see the command truth table.
/CLK CLK /CS /RAS /CAS /WE CKE A10
Chip Select : L=select, H=deselect Command Command Command Refresh Option @refresh command Precharge Option @precharge or read/write command define basic commands
Activate (ACT) [/RAS =L, /CAS =/WE =H] ACT command activates a row in an idle bank indicated by BA. Read (READ) [/RAS =H, /CAS =L, /WE =H] READ command starts burst read from the active bank indicated by BA. First output data appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (autoprecharge, READA) Write (WRITE) [/RAS =H, /CAS =/WE =L] WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write (auto-precharge, WRITEA) . Precharge (PRE) [/RAS =L, /CAS =H, /WE =L] PRE command deactivates the active bank indicated by BA. This command also terminates burst read /write operation. When A10 =H at this command, all banks are deactivated (precharge all, PREA ). Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H] REFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically.
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MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
COMMAND TRUTH TABLE
COMMAND Deselect No Operation Row Address Entry & Bank Activate Single Bank Precharge Precharge All Banks Column Address Entry & Write Column Address Entry & Write with Auto-Precharge Column Address Entry & Read Column Address Entry & Read with Auto-Precharge Auto-Refresh Self-Refresh Entry Self-Refresh Exit Burst Terminate Mode Register Set MNEMONIC DESEL NOP ACT PRE PREA WRITE CKE n-1 H H H H H H CKE n X X H H H H /CS H L L L L L /RAS X H L L L H /CAS X H H H H L /WE X H H L L L BA0,1 X X V V X V A10 /AP X X V L H L A0-9, note 11 X X V X X V
WRITEA
H
H
L
H
L
L
V
H
V
READ
H
H
L
H
L
H
V
L
V
READA REFA REFS REFSX TERM MRS
H H H L L H H
H H L H H H H
L L L H L L L
H L L X H H L
L L L X H H L
H H H X H L L
V X X X X X L
H X X X X X L
V X X X X X V 1 2
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number NOTE: 1. Applies only to read bursts with autoprecharge disabled; this command is undefined (and should not be used) for read bursts with autoprecharge enabled, and for write bursts. 2. BA0-BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0=1 , BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A11 provide the op-code to be written to the selected Mode Register.
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MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
FUNCTION TRUTH TABLE
Current State IDLE /CS /RAS /CAS /WE Address H X X XX L H H HX L L L L L L ROW ACTIVE H L L L L L L L L READ(AutoPrecharge Disabled) H L L L L L L L L H H L L L L X H H H H L L L L X H H H H L L L L H L H H L L X H H L L H H L L X H H L L H H L L BA BA, CA, A10 BA, RA BA, A10 X Op-Code, ModeL Add XX HX L BA H BA, CA, A10 L BA, CA, A10 L X H L H Command DESEL NOP TERM READ / WRITE ACT PRE / PREA REFA MRS DESEL NOP TERM READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TERM READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS Action NOP NOP ILLEGAL ILLEGAL Bank Active, Latch RA NOP Auto-Refresh Mode Register Set NOP NOP NOP Begin Read, Latch CA, Determine Auto-Precharge Begin Write, Latch CA, Determine Auto-Precharge Bank Active / ILLEGAL Precharge / Precharge All ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst Terminate Burst, Latch CA, Begin New Read, Determine AutoPrecharge ILLEGAL Bank Active / ILLEGAL Terminate Burst, Precharge ILLEGAL ILLEGAL Notes
2 2 4 5 5
H BA, RA L BA, A10 HX Op-Code, ModeL Add XX HX L BA H BA, CA, A10 L BA, CA, A10
2
3
H BA, RA L BA, A10 HX Op-Code, ModeL Add
2
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MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State WRITE(AutoPrecharge Disabled) /CS /RAS /CAS /WE Address H X X XX L L L L L L L L READ with Auto-Precharge H L L L L L L L L WRITE with Auto-Precharge H L L L L L L L L H H H H L L L L X H H H H L L L L X H H H H L L L L H H L L H H L L X H H L L H H L L X H H L L H H L L HX L BA H BA, CA, A10 L BA, CA, A10 Command DESEL NOP TERM READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TERM READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TERM READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS Action NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL Terminate Burst, Latch CA, Begin Read, Determine Auto-Precharge Terminate Burst, Latch CA, Begin Write, Determine Auto-Precharge Bank Active / ILLEGAL Terminate Burst, Precharge ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL ILLEGAL ILLEGAL Bank Active / ILLEGAL Precharge / ILLEGAL ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL ILLEGAL ILLEGAL Bank Active / ILLEGAL Precharge / ILLEGAL ILLEGAL ILLEGAL Notes
3 3 2
H BA, RA L BA, A10 HX Op-Code, ModeL Add XX HX L BA H BA, CA, A10 L BA, CA, A10 H BA, RA L BA, A10 HX Op-Code, ModeL Add XX HX L BA H BA, CA, A10 L BA, CA, A10 H BA, RA L BA, A10 HX Op-Code, ModeL Add
2 2
2 2
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MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
/CS /RAS /CAS /WE Address H X X XX L H H HX L H H L BA L H L X BA, CA, A10 L L H H BA, RA L L H L BA, A10 L L L HX Op-Code, ModeL L L L Add H X X XX ROW L H H HX ACTIVATING L H H L BA L H L X BA, CA, A10 L L H H BA, RA L L H L BA, A10 L L L HX Op-Code, ModeL L L L Add H X X XX WRITE REL H H HX COVERING L H H L BA L H L X BA, CA, A10 L L H H BA, RA L L H L BA, A10 L L L HX Op-Code, ModeL L L L Add Current State PRECHARGING Command DESEL NOP TERM READ / WRITE ACT PRE / PREA REFA MRS DESEL NOP TERM READ / WRITE ACT PRE / PREA REFA MRS DESEL NOP TERM READ / WRITE ACT PRE / PREA REFA MRS Action NOP (Idle after tRP) NOP (Idle after tRP) ILLEGAL ILLEGAL ILLEGAL NOP (Idle after tRP) ILLEGAL ILLEGAL NOP (Row Active after tRCD) NOP (Row Active after tRCD) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP NOP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Notes
2 2 2 4
2 2 2 2
2 2 2 2
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MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State /CS /RAS /CAS /WE Address REFRESHING H X X XX L L L L L L L MODE REGISTER SETTING H L L L L L L L H H H L L L L X H H H L L L L H H L H H L L X H H L H H L L H L X H L H L X H L X H L H L X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, ModeAdd X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, ModeAdd Command DESEL NOP TERM READ / WRITE ACT PRE / PREA REFA MRS DESEL NOP TERM READ / WRITE ACT PRE / PREA REFA MRS Action NOP (Idle after tRC) NOP (Idle after tRC) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP (Row Active after tRSC) NOP (Row Active after tRSC) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Notes
ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation NOTES: 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and/or data-integrity are not guaranteed.
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MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
FUNCTION TRUTH TABLE for CKE
Current State SELFREFRESHING CKE n-1 H L L L L L L POWER DOWN H L L ALL BANKS IDLE H H H H H H H L H ANY STATE other than listed above H L L CKE n X H H H H H L X H L H L L L L L L X H L H L /CS X H L L L L X X X X X L H L L L L X X X X X /RAS X X H H H L X X X X X L X H H H L X X X X X /CAS X X H H L X X X X X X L X H H L X X X X X X /WE X X H L X X X X X X X H X H L X X X X X X X Address X X X X X X X X X X X X X X X X X X X X X X INVALID Exit Self-Refresh (Idle after tRC) Exit Self-Refresh (Idle after tRC) ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self-Refresh) INVALID Exit Power Down to Idle NOP (Maintain Self-Refresh) Refer to Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer to Current State =Power Down Refer to Function Truth Table Begin CLK Suspend at Next Cycle Exit CLK Suspend at Next Cycle Maintain CLK Suspend 3 3 2 2 2 2 2 2 2 2 Action Notes 1 1 1 1 1 1 1
ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care NOTES: 1. CKE Low to High transition will re-enable CLK and other inputs asynchronously. . A minimum setup time must be satisfied before any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State. 3. Must be legal command.
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M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
SIMPLIFIED STATE DIAGRAM
POWER APPLIED
POWER ON
PREA
PRE CHARGE ALL
REFS
SELF REFRESH
MRS
REFSX REFA
MODE REGISTER SET
MRS
IDLE
AUTO REFRESH
CKEL CKEH
Active Power Down
CKEH
ACT
POWER DOWN
CKEL
ROW ACTIVE
WRITE WRITE WRITEA READA READ READ READ
BURST STOP
WRITE
READ
TERM
WRITEA READA
READA
WRITEA
PRE
PRE PRE
READA
PRE CHARGE Automatic Sequence Command Sequence
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M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or multifunctioning. 1. Apply VDD before or the same time as VDDQ 2. Apply VDDQ before or at the same time as VTT & Vref 3. Maintain stable condition for 200us after stable power and CLK, apply NOP or DSEL 4. Issue precharge command for all banks of the device 5. Issue EMRS 6. Issue MRS for the Mode Register and to reset the DLL 7. Issue 2 or more Auto Refresh commands 8. Maintain stable condition for 200 cycle After these sequence, the DDR SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register (MRS). The mode register stores these data until the next MRS command, which may be issued when both banks are in idle state. After tRSC from a MRS command, the DDR SDRAM is ready for new command.
CLK /CLK /CS /RAS /CAS /WE
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 DR 0 LTMODE BT BL
BA0 BA1 A11-A0
V
Latency Mode
CL 000 001 010 011 100 101 110 111 0 1
/CAS Latency R R 2 R R R 2.5 R NO YES
Burst Length
BL 000 001 010 011 100 101 110 111 0 1
BT=0 R 2 4 8 R R R R
BT=1 R 2 4 8 R R R R
Burst Type DLL Reset
Sequential Interleaved
R: Reserved for Future Use
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MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
EXTENDED MODE REGISTER
DLL disable / enable mode can be programmed by setting the extended CLK mode register (EMRS). The extended mode register stores these data /CLK until the next EMRS command, which may be issued when all banks are in idle state. After tRSC from a EMRS command, the DDR SDRAM is /CS ready for new command.
/RAS /CAS
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 0
QFC DS DD
/WE BA0 BA1 A11-A0
V
DLL Disable Drive Strength QFC 0 1 0 1
0 1
DLL Enable DLL Disable Normal Weak
Disable Enable
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M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
/CLK CLK Command Address DQS DQ CL= 2 BL= 4 /CAS Latency
Q0 Q1 Q2 Q3 D0 D1 D2 D3 Read Y Write Y
Burst Length
Burst Length
Initial Address A2 0 0 0 0 1 1 1 1 A1 A0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1
BL Sequential 0 1 2 3 8 4 5 6 7 0 1 4 2 3 0 2 1 1 2 3 4 5 6 7 0 1 2 3 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 3 4 5 6 7 0 1 2 3 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4
Column Addressing Interleaved 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 0 1 2 3 0 1 1 0 3 2 5 4 7 6 1 0 3 2 1 0 2 3 0 1 6 7 4 5 2 3 0 1 3 2 1 0 7 6 5 4 3 2 1 0 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0
0 1 0 1 0 1 0 1 0 1
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M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
ABSOLUTE MAXIMUM RATINGS
Symbol Vdd VddQ VI VO IO Pd Topr Tstg Parameter Supply Voltage Supply Voltage for Output Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature Ta = 25 C
o
Conditions with respect to Vss with respect to VssQ with respect to Vss with respect to VssQ
Ratings -0.5 ~ 3.7 -0.5 ~ 3.7 -0.5 ~ Vdd+0.5 -0.5 ~ VddQ+0.5 50 1000 0 ~ 70 -65 ~ 150
Unit V V V V mA mW
o o
C C
DC OPERATING CONDITIONS
(Ta=0 ~ 70oC, unless otherwise noted)
S ym bol
P a ra m e te r
V dd S upply V olta ge V ddQ S upply V olta ge for O utput V re f Input R e fe re nc e V olta ge V IH (D C ) H igh-L e ve l Input V olta ge V IL (D C ) L ow -L e ve l Input V olta ge V IN (D C ) Input V olta ge L e ve l, C L K a nd /C L K V ID (D C ) Input D iffe re ntia l V olta ge , C L K a nd /C L K V TT I/O T e rm ina tion V olta ge
M in. 2.3 2.3 0.49*V ddQ V re f + 0.18 -0.3 -0.3 0.36 V re f - 0.04
L im its T yp. 2.5 2.5 0.50*V ddQ
M a x. 2.7 2.7 0.51*V ddQ V ddQ +0.3 V re f - 0.18 V ddQ + 0.3 V ddQ + 0.6 V re f + 0.04
U nit N ote s V V V V V V V V
5
7 6
CAPACITANCE
(Ta=0 ~ 70oC, Vdd = VddQ = 2.5V + 0.2V, Vss = VssQ = 0V, unless otherwise noted)
Symbol CI(A) CI(C) CI(K) CI/O CO(QF)
Parameter Input Capacitance, address pin Input Capacitance, control pin Input Capacitance, CLK pin I/O Capacitance, I/O, DQS, DM pin Output Capacitance, /QFC
Test Condition
VI=1.25v f=100MHz VI=25mVrms
Limits Delta Unit Notes Min. Max. Cap.(Max.) 2.0 3.0 pF 11 0.50 2.0 3.0 pF 11 2.0 3.0 0.25 pF 11 4.0 5.0 pF 11 0.50 2.0 3.0 pF 11
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M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~ 70oC, Vdd = VddQ = 2.5V + 0.2V, Vss = VssQ = 0V, Output Open, unless otherwise noted)
Symbol Parameter/Test Conditions Organization x4 x8 x16 x4 x8 x16 x4/x8/x16 Limits(Max.) -75 -10 105 110 120 110 115 135 20 95 105 115 100 110 130 20 Unit Notes
OPERATING CURRENT: One Bank; Active-Precharge; t RC = t RC MIN; t CK IDD0 = t CK MIN; DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle OPERATING CURRENT: One Bank; Active-Read-Precharge; IDD1 Burst = 2; t RC = t RC MIN; CL = 2.5; t CK = t CK MIN; IOUT= 0mA; Address and control inputs changing once per clock cycle IDD2P PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; powerdown mode; CKE IDLE STANDBY CURRENT: /CS > VIH (MIN); All banks idle; IDD2N CKE > VIH (MIN); t CK = t CK MIN; Address and other control inputs changing once per clock cycle IDD3P ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; powerdown mode; CKE < VIL (MAX); t CK = t CK MIN
x4/x8/x16
40
40
x4/x8/x16 x4 x8 x16 x4 x8 x16 x4 x8 x16 x4/x8/x16 x4/x8/x16
40 60 65 75 150 170 210 145 165 200 190 3
40 55 60 70 140 160 200 135 155 180 180 3
mA
ACTIVE STANDBY CURRENT: /CS > VIH (MIN); CKE > VIH (MIN); One bank; Active-Precharge; t RC = t RAS MAX; t CK = t CK MIN; DQ,DM and IDD3N DQS inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst;One bank active; IDD4R Address and control inputs changing once per clock cycle;CL=2.5; t CK = t CK MIN; IOUT = 0 mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; IDD4W Address and control inputs changing once per clock cycle; CL=2.5; t CK = t CK MIN;DQ, DM and DQS inputs changing twice per clock cycle IDD5 AUTO REFRESH CURRENT: t RC = t RFC (MIN) IDD6 SELF REFRESH CURRENT: CKE < 0.2V
9
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70oC, Vdd = VddQ = 2.5V + 0.2V, Vss = VssQ = 0V, Output Open, unless otherwise noted)
S ymb o l P a ra me ter / Test C o nd itio ns Limits M in. V ref + 0 .3 5 M ax. V ref - 0 .3 5 0 .7 V d d Q + 0 .6 0 .5 * V d d Q - 0 .2 0 .5 * V d d Q + 0 .2 -5 5 -2 2 - 1 6 .8 1 6 .8 U nit V V V V A A mA mA 7 8 N o tes
V IH (A C ) H igh- Level Inp ut V o ltage (A C ) V IL(A C ) Lo w - Level Inp ut V o ltage (A C ) V ID (A C ) V IX (A C ) IO Z II IO H IO L Inp ut D ifferential V o ltage, C LK and /C LK Inp ut C ro ssing P o int V o ltage, C LK and /C LK O ff- state O utp ut C urrent /Q flo ating V o = 0 ~ V d d Q Inp ut C urrent / V IN = 0 ~ V d d Q O utp ut H igh C urrent (V O U T = 1 .9 5 V ) O utp ut H igh C urrent (V O U T = 0 .3 5 V )
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DDR SDRAM (Rev.0.1) Jun,'00 Preliminary
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
AC TIMING REQUIREMENTS
(Ta=0 ~ 70oC, Vdd = VddQ = 2.5V +0.2V, Vss = VssQ = 0V, unless otherwise noted)
Symbol tAC AC Characteristics Parameter DQ Output Valid data delay time from CLK//CLK -75 Min. -0.75 -0.75 0.45 0.45 7.5 10 0.5 0.5 1.75 -0.75 -0.75 -0.5 tCLmin or tCHmin tHP-0.75 0.75 0.35 0.35 0.2 0.2 15 0 0.4 0.25 0.9 0.9 0.4 0.9 0.4 0.9 0.6 1.1 0.6 1.1 4 1.25 2 1.25 0.6 1.25 0.75 0.75 0.5 Max 0.75 0.75 0.55 0.55 15 15 Min. -0.8 -0.8 0.45 0.45 8 10 0.6 0.6 2 -0.8 -0.8 -0.6 tCLmin or tCHmin tHP-1.0 0.75 0.35 0.35 0.2 0.2 15 0 0.4 0.25 1.2 1.2 0.4 0.9 0.4 0.9 0.6 1.1 0.6 1.1 4 2 0.6 1.25 0.8 0.8 0.6 -10 Max 0.8 0.8 0.55 0.55 15 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns tCK tCK tCK tCK tCK ns ns tCK tCK ns ns tCK tCK tCK tCK ns ns 19 19 16 15 14 14 Notes
tDQSCK DQ Output Valid data delay time from CLK//CLK tCH tCL tCK tDH tDS tDIPW tHZ tLZ CLK High level width CLK Low level width CLK cycle time Input Setup time (DQ,DM) Input Hold time(DQ,DM) DQ and DM input pulse width (for each input) Data-out-high impedance time from CLK//CLK Data-out-low impedance time from CLK//CLK
tDQSQ DQ Valid data delay time from DQS tHP tQH tDQSS Clock half period Output DQS valid window Write command to first DQS latching transition
tDQSH DQS input High level width tDQSL DQS input Low level width tDSS tDSH tMRD DQS falling edge to CLK setup time DQS falling edge hold time from CLK Mode Register Set command cycle time
tWPRES Write preamble setup time tWPST Write postamble tWPRE Write preamble tIS tIH tRPST tRPRE tQPST Input Setup time (address and control) Input Hold time (address and control) Read postamble Read preamble /QFC postamble during reads
tQPRE /QFC preamble during reads tQCK tQOH /QFC output access time from CLK//CLK, for write /QFC output hold time for writes
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DDR SDRAM (Rev.0.1) Jun,'00 Preliminary
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
AC TIMING REQUIREMENTS(Continues)
(Ta=0 ~ 70oC, Vdd = VddQ = 2.5V +0.2V, Vss = VssQ = 0V, unless otherwise noted)
Symbol tRAS tRC tRFC tRCD tRP tRRD tWR tDAL tWTR AC Characteristics Parameter Row Active time Row Cycle time(operation) Auto Ref. to Active/Auto Ref. command period Row to Column Delay Row Precharge time Act to Act Delay time Write Recovery time Auto Precharge write recovery + precharge time Internal Write to Read Command Delay -75 Min. 45 65 75 20 20 15 15 35 1 75 200 1 1 15.6 Max 120,000 Min. 50 70 80 20 20 15 15 35 1 80 200 1 1 15.6 -10 Max 120,000 Unit ns ns ns ns ns ns ns ns tCK ns tCK tCK tCK s 18 17 Notes
tXSNR Exit Self Ref. to non-Read command tXSRD Exit Self Ref. to -Read command tXPNR Exit Power down to command tXPRD Exit Power down to -Read command tREFI Average Periodic Refresh interval
Output Load Condition
DQS
VTT=VREF 50 VOUT Zo=50 30pF VREF
VREF
DQ
VREF
Output Timing Measurement Reference Point
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DDR SDRAM (Rev.0.1) Jun,'00 Preliminary
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
Notes 1. All voltages referenced to Vss. 2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK//CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL(AC) and VIH(AC). 4. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above (below) the DC input LOW (HIGH) level. 5. VREF is expected to be equal to 0.5*VddQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +2% of the DC value. 6. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 7. VID is the magnitude of the difference between the input level on CLK and the input level on /CLK. 8. The value of VIX is expected to equal 0.5*VddQ of the transmitting device and must track variations in the DC level of the same. 9. Enables on-chip refresh and address counters. 10. IDD specifications are tested after the device is properly initialized. 11. This parameter is sampled. VddQ = 2.5V+0.2V, Vdd = 2.5V + 0.2V , f = 100 MHz, Ta = 25oC, VOUT(DC) = VddQ/2, VOUT(PEAK TO PEAK) = 25mV. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in loading (to facilitate trace matching at the board level). 12. The CLK//CLK input reference level (for timing referenced to CLK//CLK) is the point at which CLK and /CLK cross; the input reference level for signals other than CLK//CLK, is VREF. 13. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE< 0.3VddQ is recognized as LOW. 14. t HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ), or begins driving (LZ). 15. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 16. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CLK edge. A valid transition is defined as monotonic, and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 17. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. 18. tXPRD should be 200 tCLK in the condition of the unstable CLK operation during the power down mode. 19. For command/address and CK & /CK slew rate > 1.0V/ns.
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DDR SDRAM (Rev.0.1) Jun,'00 Preliminary Read Operation
tCK tCH tCL
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
/CLK CLK Cmd & Add.
tDQSCK tIS tIH VREF
Valid Data tRPST
DQS /QFC DQ
tRPRE
tQPST tQPRE tQH tAC tDQSQ
Write Operation / tDQSS=max. /CLK CLK DQS
tQCK tDQSS tWPRES tDSS tDQSL tDS tDQSH tDH tWPST
/QFC
tWPRE
tQOH(min)
DQ Write Operation / tDQSS=min. /CLK CLK DQS /QFC
tDQSS tWPRES tWPRE tDQSL tDS tDQSH tDH tQOH(max) tDSH tWPST tQCK
DQ
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DDR SDRAM (Rev.0.1) Jun,'00 Preliminary OPERATIONAL DESCRIPTION BANK ACTIVATE
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
The DDR SDRAM has four independent banks. Each bank is activated by the ACT command with the bank addresses (BA0,1). A row is indicated by the row address A11-0. The minimum activation interval between one bank and the other bank is tRRD. Maximum 2 ACT commands are allowed within tRC,although the number of banks which are active concurrently is not limited. PRECHARGE The PRE command deactivates the bank indicated by BA0,1. When multiple banks are active, the precharge all command (PREA,PRE+A10=H) is available to deactivate them at the same time. After tRP from the precharge, an ACT command to the same bank can be issued.
Bank Activation and Precharge All (BL=8, CL=2)
/CLK CLK
2 ACT command / tRCmin tRCmin
Command A0-9,11
ACT tRRD Xa
ACT READ tRAS Xb tRCD Y BL/2 0
PRE tRP
ACT
Xb
A10 BA0,1
Xa
Xb
1
Xb
00
01
00
01
DQS
DQ
Qa0
Qa1
Qa2
Qa3
Qa4
Qa5
Qa6
Qa7
Precharge all
A precharge command can be issued at BL/2 from a read command without data loss.
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DDR SDRAM (Rev.0.1) Jun,'00 Preliminary READ
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
After tRCD from the bank activation, a READ command can be issued. 1st Output data is available after the /CAS Latency from the READ, followed by (BL-1) consecutive data when the Burst Length is BL. The start address is specified by A11,A9-A0(x4)/A9-A0(x8)/A8-A0(x16), and the address sequence of burst data is defined by the Burst Type. A READ command may be applied to any active bank, so the row precharge time (tRP) can be hidden behind continuous output data by interleaving the multiple banks. When A10 is high at a READ command, the auto-precharge (READA) is performed. Any command(READ,WRITE,PRE,ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at BL/2 after READA. The next ACT command can be issued after (BL/2+tRP) from the previous READA.
Multi Bank Interleaving READ (BL=8, CL=2)
/CLK CLK Command A0-9,11 A10 BA0,1 DQS DQ
/CAS latency
Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7 Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Qb7 Qb8
ACT tRCD Xa Xa
READ ACT Y 0 Xb Xb
READ PRE Y 0 0
00
00
10
10
00
Burst Length
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DDR SDRAM (Rev.0.1) Jun,'00 Preliminary
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM READ with Auto-Precharge (BL=8, CL=2)
/CLK CLK
BL/2 + tRP
Command A0-9,11 A10 BA0,1 DQS DQ
ACT tRCD Xa Xa 00
READ BL/2 Y 1 00 tRP
ACT Xb Xb 00
Qa0
Qa1
Qa2
Qa3
Qa4
Qa5
Qa6
Qa7
Internal precharge start
READ Auto-Precharge Timing (BL=8)
/CLK CLK Command
ACT READ BL/2
CL=2.5 DQ
Qa0
Qa1
Qa2
Qa3
Qa4
Qa5
Qa6
Qa7
CL=2 DQ
Qa0
Qa1
Qa2
Qa3
Qa4
Qa5
Qa6
Qa7
Internal Precharge Start Timing
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DDR SDRAM (Rev.0.1) Jun,'00 Preliminary
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
WRITE After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set from the WRITE command with data strobe input, following (BL-1) data are written into RAM, when the Burst Length is BL. The start address is specified by A11,A9-A0(x4)/A9-A0(x8)/A8-A0(x16), and the address sequence of burst data is defined by the Burst Type. A WRITE command may be applied to any active bank, so the row precharge time (tRP) can be hidden behind continuous input data by interleaving the multiple banks. From the last data to the PRE command, the write recovery time (tWRP) is required. When A10 is high at a WRITE command, the auto-precharge(WRITEA) is performed. Any command(READ,WRITE,PRE,ACT) to the same bank is inhibited till the internal precharge is complete. The next ACT command can be issued after tDAL from the last input data cycle. Multi Bank Interleaving WRITE (BL=8)
/CLK CLK Command A0-9,11 A10 BA0,1 DQS DQ
Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7 Db0 Db1 Db2 Db3 Db4 Db5 Db6 Db7
ACT tRCD Xa D Xa Xa 00
WRITE ACT Ya 0 00 Xb Xb 10 tRCD D
WRITE Yb 0 10
PRE
PRE
0 00
0 10
WRITE with Auto-Precharge (BL=8)
/CLK CLK Command A0-9,11 A10 BA0,1 DQS DQ
Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7
ACT tRC Xa Xa 00 D
WRITE tDAL Y 1 00
ACT Xb Xb 00
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DDR SDRAM (Rev.0.1) Jun,'00 Preliminary
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
BURST INTERRUPTION
[Read Interrupted by Read] Burst read operation can be interrupted by new read of any bank. Random column access is allowed. READ to READ interval is minimum 1CLK. Read Interrupted by Read (BL=8, CL=2)
/CLK CLK Command A0-9,11 A10 BA0,1 DQS DQ
Qai0 Qai1 Qaj0 Qaj1 Qaj2 Qaj3 Qak0 Qak1 Qak2 Qak3 Qak4 Qak5 Qal0 Qal1 Qal2 Qal3 Qal4 Qal5 Qal6 Qal7
READ READ Yi 0 00 Yj 0 00
READ Yk 0 10
READ Yl 0 01
[Read Interrupted by precharge] Burst read operation can be interrupted by precharge of the same bank. READ to PRE interval is minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency. As a result, READ to PRE interval determines valid data length to be output. The figure below shows examples of BL=8. Read Interrupted by Precharge (BL=8)
/CLK CLK Command DQS DQ Command
READ PRE
Q0 Q1 Q2 Q3 Q4 Q5
READ
PRE
CL=2.5
DQS DQ Command DQS DQ
Q0 Q1 Q0 Q1 Q2 Q3
READ PRE
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DDR SDRAM (Rev.0.1) Jun,'00 Preliminary
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM Read Interrupted by Precharge (BL=8)
/CLK CLK
Command DQS DQ Command
READ
PRE
Q0
Q1
Q2
Q3
Q4
Q5
READ
PRE
CL=2.0
DQS DQ Command DQS DQ
Q0 Q1 Q0 Q1 Q2 Q3
READ PRE
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DDR SDRAM (Rev.0.1) Jun,'00 Preliminary
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
[Read Interrupted by Burst Stop] Burst read operation can be interrupted by a burst stop command(TERM). READ to TERM interval is minimum 1 CLK. A TERM command to output disable latency is equivalent to the /CAS Latency. As a result, READ to TERM interval determines valid data length to be output. The figure below shows examples of BL=8.
Read Interrupted by TERM (BL=8)
/CLK CLK Command DQS DQ Command
READ
TERM
Q0 Q1 Q2 Q3 Q4 Q5
READ
TERM
CL=2.5
DQS DQ Command DQS DQ Command DQS DQ Command
READ
Q0 Q1 Q2 Q3 Q4 Q5 Q0 Q1 Q0 Q1 Q2 Q3
READ TERM
READ
TERM
TERM
CL=2.0
DQS DQ Command DQS DQ
Q0 Q1 Q0 Q1 Q2 Q3
READ TERM
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DDR SDRAM (Rev.0.1) Jun,'00 Preliminary
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
[Read Interrupted by Write with TERM] Read Interrupted by TERM (BL=8)
/CLK CLK Command
READ TERM WRITE
CL=2.5
DQS DQ Command
READ TERM
Q0 Q1 Q2 Q3 D0 D1 D2 D3 D4 D5
WRITE
CL=2.0
DQS DQ
Q0 Q1 Q2 Q3 D0 D1 D2 D3 D4 D5 D6 D7
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DDR SDRAM (Rev.0.1) Jun,'00 Preliminary [Write interrupted by Write]
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
Burst write operation can be interrupted by write of any bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CLK. Write Interrupted by Write (BL=8)
/CLK CLK Command A0-9,11 A10 BA0,1 DQS DQ
Dai0 Dai1 Daj0 Daj1 Daj2 Daj3 Dak0 Dak1 Dak2 Dak3 Dak4 Dak5 Dal0 Dal1 Dal2 Dal3 Dal4 Dal5 Dal6 Dal7
WRITE WRITE Yi Yj
WRITE Yk
WRITE Yl
0 00
0 00
0 10
0 00
[Write interrupted by Read] Burst write operation can be interrupted by read of the same or the other bank. Random column access is allowed. Internal WRITE to READ command interval(tWTR) is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is "don't care". tWTR is referenced from the first positive edge after the last data input. Write Interrupted by Read (BL=8, CL=2.5)
/CLK CLK Command A0-9,11 A10 BA0,1 DM tWTR QS DQ
Dai0 Dai1 Qaj0 Qaj1 Qaj2 Qaj3 Qaj4 Qaj5 Qaj6 Qaj7
WRITE Yi 0 00
READ Yj 0 00
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DDR SDRAM (Rev.0.1) Jun,'00 Preliminary
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
[Write interrupted by Precharge] Burst write operation can be interrupted by precharge of the same or all bank. Random column access is allowed. tWR is referenced from the first positive CLK edge after the last data input. Write Interrupted by Precharge (BL=8, CL=2.5)
/CLK CLK Command A0-9,11 A10 BA0,1 DM QS DQ
Dai0 Dai1
WRITE Yi 0 00
PRE
00
tWR
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DDR SDRAM (Rev.0.1) Jun,'00 Preliminary [Initialize and Mode Register sets] Initialize and MRS
/CLK CLK CKE Command A0-9,11 A10 BA0,1 DQS DQ tMRD
Extended Mode Register Set 1 NOP PRE EMRS
Code
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
MRS
Code
PRE
AR
AR
MRS
ACT
Xa
Code
Code
1
Code
Xa
10
00
00
Xa
tMRD
tRP
tRFC
tRFC
tMRD
Mode Register Set, Reset DLL
[AUTO REFRESH] Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,/WE=CKE=H) command. The refresh address is generated internally. 4096 REFA cycles within 64ms refresh 128Mbits memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing an auto refresh, all banks must be in the idle state. Auto-refresh to auto-refresh interval is minimum tRFC . Any command must not be supplied to the device before tRFC from the REFA command. Auto-Refresh
/CLK CLK /CS /RAS /CAS /WE CKE A0-11 BA0,1
tRFC NOP or DESELECT
Auto Refresh on All Banks
Auto Refresh on All Banks 32
MITSUBISHI ELECTRIC
DDR SDRAM (Rev.0.1) Jun,'00 Preliminary
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
[SELF REFRESH] Self -refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,/WE=H,CKE=L). Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the selfrefresh mode, CKE is asynchronous and the only enable input, all other inputs including CLK are disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting CKE for longer than tXSNR/tXSRD. Self-Refresh
/CLK CLK /CS /RAS /CAS /WE CKE A0-11 BA0,1
X X tXSNR Self Refresh Exit tXSRD
Y Y
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DDR SDRAM (Rev.0.1) Jun,'00 Preliminary
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
[Asynchronous SELF REFRESH] Asynchronous Self -refresh mode is entered by CKE=L within 2 tCLK after issuing a REFA command (/CS=/RAS=/CAS=L,/WE=H). Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode, CKE is asynchronous and the only enable input, all other inputs including CLK are disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting CKE for longer than tXSNR/tXSRD.
Asynchronous Self-Refresh
/CLK CLK /CS /RAS /CAS /WE CKE A0-11 BA0,1
max 2 tCLK
tXSNR Self Refresh Exit
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DDR SDRAM (Rev.0.1) Jun,'00 Preliminary
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
[Power DOWN] The purpose of CLK suspend is power down. CKE is synchronous input except during the selfrefresh mode. A command at cycle is ignored. From CKE=H to normal function, DLL recovery time is NOT required in the condition of the stable CLK operation during the power down mode. Power Down by CKE
/CLK CLK CKE Command
PRE NOP
Standby Power Down
NOP
Valid
tXPNR/tXPRD CKE Command Active Power Down
ACT
NOP
NOP
Valid
[DM CONTROL] DM is defined as the data mask for writes. During writes,DM masks input data word by word. DM to write mask latency is 0. DM Function(BL=8,CL=2)
/CLK CLK Command DM DQS DQ
D0 D1 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6
WRITE
READ
Don't Care
masked by DM=H
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DDR SDRAM (Rev.0.1) Jun,'00 Preliminary
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
Keep safety first in your circuit designs! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
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